High power field-effect transistors (FETs), such as gallium nitride (GaN) based heterostructure field effect transistors (HFETs), feature increasingly high powers and breakdown voltages. Although these features make such devices extremely promising for various applications in power electronics, certain material and device specifics significantly limit their performance characteristics.
On important limitation of GaN-based HFETs, as well as other FETs operating at high voltage, is a non-uniform electric field profile present in the gate-drain spacing. FIG. 1 shows a conventional heterostructure FET (HFET) 2 according to the prior art, and FIG. 2 shows an illustrative electric field distribution chart according to the prior art. As illustrated in FIG. 2, the electric field profile in the gate-drain spacing having a distance, LGD, shown in FIG. 1 exhibits a strong peak near the gate edge when the HFET 2 is operated as a switch (without field plate). The peak width is defined by the carrier concentration in the channel. To this extent, a breakdown voltage for the HFET 2 does not increase when the gate-drain spacing distance LGD is increased.
One approach to lower the peak electric field near the gate edge is the use of one or more field-modulating plates (FPs), which can be connected to either the gate, source, or drain electrode. FIG. 2 illustrates an illustrative field plate connected to a gate and the resulting electric field distribution. A multistep field plate structure is shown in FIG. 3, and a gradual field plate structure is shown in FIG. 4. In each case, the field plate structure decreases the peak field near the gate electrode edge by splitting it into two or more peaks, thereby increasing the breakdown voltage for the device. However, even multiple field plate structures cannot achieve a uniform electric field in the device channel. Additionally, these approaches can degrade performance due to excessive capacitances associated with the field-plate electrodes.